1. Field of the Invention
The present invention relates to a semiconductor device and a method of controlling the same, and particularly relates to a semiconductor device that generates an internal voltage from an external power supply voltage and a method of controlling the same.
2. Description of Related Art
In some of the semiconductor devices such as a DRAM (Dynamic Random Access Memory), two regulators are employed in an internal voltage generating circuit which generates an internal voltage from an external power supply voltage. One of them is a stand-by regulator whose current supply capability is small and a power consumption is also small, and another one of them is an active regulator whose current supply capability and power consumption are both large. Such a configuration is employed primarily from a viewpoint of reducing the power consumption, where the stand-by regulator is configured to operate constantly during when a power of the semiconductor device is on, whereas the active regulator is configured to operate only during an active period.
A regulator is generally configured by including an operational amplifier and a driver transistor. An activation of the active regulator is performed by turning on a current supplying transistor provided in a common source of the operational amplifier. When the current supplying transistor is turned on, a current flows in a current mirror circuit in the operational amplifier and thereby the driver transistor turns on, and the internal voltage begins to be generated. Japanese Patent Application Laid-open Nos. H05-62481, 2001-84765 and H11-96758 disclose examples of a voltage generating circuit that performs such an activation control.
In the voltage generating circuit described in Japanese Patent Application Laid-open No. H05-62481, two current supplying transistors are provided in parallel, and one of the current supplying transistors is configured to turn on only for a predetermined period of time upon a switchover from a stand-by to being active. By employing such a configuration, as is described in paragraph [0007] of Japanese Patent Application Laid-open No. H05-62481, it becomes possible to suppress a drop in the internal voltage just after the switchover as possible, and also to suppress an overshoot in the internal voltage due to a reaction after the drop.
However, in the aforementioned configuration, there is a problem that another overshoot (in a case where the driver transistor is an N-type channel MOS transistor) or an undershoot (in a case where the driver transistor is a P-type channel MOS transistor) occurs in the internal voltage just after the one of the current supplying transistors is turned off. This is because a gate potential of the driver transistor temporarily rises due to the current supplying transistor being abruptly turned off, and a suppression of such an overshoot or an undershoot is being required.